1. Field of the Invention
The present invention relates to an etching process with a conductive mask, more particular to, an etching process using a conductive mask to disperse electric charges caused from the dry etching process.
2. Description of the Prior Art
The semiconductor manufacture is more precise makes the integrated circuit has a revolution. The function and memory of the computer advance soon, and the peripheral industry develops, too. The semiconductor industry just likes Mor law forecasts the number of the transistor on the integrated circuit becomes double in eighteen months. So, the manufacture is more precise. The window process of the semiconductor was 0.18 mm in 1999, 0.13 mm in 2001, 90 nm in 2003 (0.09 mm), and now is 65 nm in 2005 (0.065 mm).
The contact plug and via plug always are the important technology in the semiconductor manufacture. The contact plug and via plug are able to electrically connect with the transistor, capacitor, the multilevel interconnects to form the whole integrated circuit. Except tungsten (W) and aluminum (Al) alloy can be the material of the contact plug and the via plug, the cooper process is a choice, too. When copper is the material of the multilevel interconnects, the via plug and the copper line need to be complete by the single damascene or the dual damascene, because copper can't be etched easily. But, the dry etching process of the contact hole, the via hole, or the trench causes a lot of electric charges on the dielectric layer. When the metal layer or the components almost are etched or already are etched, the metal layer under the dielectric layer or the components will burst, that causes the yield decreases.
Please refer to FIG. 1. FIG. 1 is a diagram of a metal layer bursts caused by an etching process in the prior art. As FIG. 1 shows, a semiconductor wafer 100 comprises a NMOS and a PMOS individually on the P well 102 and N well 104 of the P semiconductor substrate 101. A STI (shallow trench isolation) 106 surrounds NMOS and PMOS to divide each NMOS and PMOS. Each PMOS and NMOS comprises a gate 108, 109, and source/drain 110, 111 on the P well 102 and N well 104.
Then, a contact etch stop layer (CESL) 113, an undoped silica glass (USG) 112, and a phosphorus-doped silica glass (PSG) 114 are doped on P semiconductor substrate 101 and cover the gate 108, 109, source/drain 110, 111, STI 106, P well 102, and N well 104. For the multilevel interconnects electrically connect with the NMOS, PMOS, and other components, a contact plug 116 is formed by the lithograph process, the etching process, the doping process, and CMP. The one end of contact plug 116 contacts with the gate 108, or with the source/drain 110. The other end contacts with a metal layer 118. The metal layer 118 is patterned and is doped a dielectric layer 120. The dielectric layer 120 could comprise an HDP oxide 119 is formed by HDPCVD, a PE oxide 121 is formed by PECVD on the dielectric layer, and an cap oxide 123 on the an PB oxide 121, as the individual manufacture demands.
As FIG. 1 shows, a photoresist 122 is added on the dielectric layer 120, after PEP, the pattern photoresist 122 is produced, the dry etching process is performed to form a via hole 124 in the dielectric layer 120. In recently technology, the plasma dry etching process always applies with the via hole etching process. But, the dry etching process causes a lot of charges, and the charges store in the dielectric layer 120. So, when the via hole etching process almost or already etches till the metal layer 118 surface, the stored charges will lead off, and will cause the metal layer 118 to form a burst 125. Furthermore, the gate 108 or others component will burst.
So, how to avoid the via hole dry etching process is to induce the metal burst, which is an important issue in this domain.